Power - Aware Mobile Sensor Networks with Reconfigurable Computing Nodes
Author | : Reno Massarini |
Publisher | : |
Total Pages | : 75 |
Release | : 2006 |
ISBN-10 | : OCLC:80234978 |
ISBN-13 | : |
Rating | : 4/5 (78 Downloads) |
Book excerpt: Portable electronic devices like laptops, PDAs, and cell phones are finding their way into more and more homes, offices, and classrooms. They typically come with batteries, wireless networking hardware, and a variety of options for connecting to a network (like radio frequency and infrared). The heart of a portable electronic device is generally an ASIC or a microprocessor. Portable electronic devices can form mobile wireless networks when traditional wired networks are down or non-existent. We want to maximize the lifetime of those networks without sacrificing a large amount of their processing performance. That is accomplish in this thesis by substituting an FPGA for an ASIC or a microprocessor in the portable electronic devices. An FPGA has the ability to implement many different versions of an application (called design points in this thesis) on its hardware. The differences between those design points are that devices power consumption and processing performance. Having many design points helps an FPGA maximize its battery lifetime without sacrificing a large amount of its processing performance. But, a microprocessor can now use a low power architecture or it can scale its frequency and voltage, thus creating several possible design points. In this thesis, a design point for a microprocessor is a version of an application with a specified frequency and voltage. A mobile wireless sensor network using FPGA based nodes with 16 design points generated 3 times more packets compared to a mobile wireless sensor network using microprocessor based nodes with 4 design points. Its base station received 5 times more packets. Simulations using that network ran 2 times longer.