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Energy-Efficient VLSI Architectures for Real-Time and 3D Video Processing

Download or Read eBook Energy-Efficient VLSI Architectures for Real-Time and 3D Video Processing PDF written by Michael Stefano Fritz Schaffner and published by BoD – Books on Demand. This book was released on 2018-10-24 with total page 294 pages. Available in PDF, EPUB and Kindle.
Energy-Efficient VLSI Architectures for Real-Time and 3D Video Processing
Author :
Publisher : BoD – Books on Demand
Total Pages : 294
Release :
ISBN-10 : 9783866286245
ISBN-13 : 3866286244
Rating : 4/5 (45 Downloads)

Book Synopsis Energy-Efficient VLSI Architectures for Real-Time and 3D Video Processing by : Michael Stefano Fritz Schaffner

Book excerpt: Multiview autostereoscopic displays (MADs) make it possible to view video content in 3D without wearing special glasses, and such displays have recently become available. The main problem of MADs is that they require several (typically 8 or 9) views, while most of the 3D video content is in stereoscopic 3D today. To bridge this content-display gap, the research community started to devise automatic multiview synthesis (MVS) methods. Common MVS methods are based on depth-image-based rendering, where a dense depth map of the scene is used to reproject the image to new viewpoints. Although physically correct, this approach requires accurate depth maps and additional inpainting steps. Our work uses an alternative conversion concept based on image domain warping (IDW) which has been successfully applied to related problems such as aspect ratio retargeting for streaming video, and dispa- rity remapping for depth adjustments in stereoscopic 3D content. IDW shows promising performance in this context as it only requires robust, sparse point- correspondences and no inpainting steps. However, MVS, using IDW as well as alternative approaches, is computationally demanding and requires realtime processing - yet such methods should be portable to end-user and even mobile devices to develop their full potential. To this end, this thesis investigates efficient algorithms and hardware architectures for a variety of subproblems arising in the MVS pipeline.


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