Book excerpt: On-chip memory arrays are widely used in systems-on-chip. Prior research has shown that timing critical paths often go through these memories. Embedded memories are typically tested using memory built-in self-test and macro test. However, these techniques have relatively low small delay fault coverage, so functional test must be used to accurately determine maximum operating frequency. In this work we achieve high delay fault coverage by testing the timing critical paths in and out of embedded memories, including the paths in the surrounding logic. We use our prior work on pseudo functional K longest path per gate test generation and extend it to handle memory test. In pseudo functional test, low-speed preamble cycles are used to stabilize the supply voltage before the at-speed launch and capture cycles. Since the memory cells are non-scan, a value that is captured in the memory must be moved to a scan cell using low-speed coda cycles. This approach tests any path through a non-scan latch. Our approach eliminates the coverage "shadows" around embedded memories and non-scan latches. We have established a flow to test industrial circuits with embedded memory. Industrial circuits with different size memory arrays are used to justify the efficiency of the flow. Our results demonstrate that we can effectively generate patterns that cover paths in and out of the memories. The electronic version of this dissertation is accessible from http://hdl.handle.net/1969.1/155297